Phase detectors can be found in various electronic circuits and systems including telecommunication and computer systems as well as semiconductor memories. A common application for phase detectors is in signal sampling to facilitate synchronous interface between circuits. For optimum sampling of an input data, it is desirable to have the sampling clock in quadrature phase with respect to the input data. Two signals are said to be in quadrature if they are 90 degrees out of phase. As shown in FIG. 1, signals SIG1 and SIG2 operate at the same frequency and each has a duty cycle of 50% and are in quadrature. The rising edge of signal SIG2 thus occurs at exactly the mid point of the signal SIG1 pulse.
A simplified example of a quadrature phase detector circuit is shown in FIG. 2. As depicted in FIG. 2, circuit 10 includes a first capacitive element C1 coupled between ground and node N and a second capacitive element C2 coupled between ground and node P. A switch S1 is coupled between node N and node 20 and a switch S2 is coupled between node P and node 20. A current source 26 coupled between node 20 and ground provides a bias current I for the circuit.
The two input signals SIG1 and SIG2 as shown in FIG. 1 are applied to and control the opening and closing of switches S1 and S2, respectively. The switches are controlled such that switch S1 is closed and switch S2 is open during time interval .DELTA.T.sub.1, and switch S1 is open and switch S2 is closed during time interval .DELTA.T.sub.2. During time interval .DELTA.T.sub.1, when switch S1 is closed and switch S2 is open, circuit 10 of FIG. 1 reduces to circuit 10' depicted in FIG. 3a. Circuit 10' is essentially an integrator circuit, and assuming a linear operation, the voltage at node N (V.sub.N) is given by: EQU .DELTA.V.sub.N =-(I/C1).DELTA.T.sub.1 Equation 1
During time interval .DELTA.T.sub.2, when switch S1 is open and switch S2 is closed, circuit 10 of FIG. 2 reduces to circuit 10" depicted in FIG. 3b. Circuit 10" also forms an integrator with the voltage at node P (V.sub.P) determined by: EQU .DELTA.V.sub.P =-(I/C2).DELTA.T.sub.2 Equation 2
If the capacitors C1 and C2 are equal in value (i.e. C1=C2=C), then equations 1 and 2 reduce to: EQU .DELTA.V.sub.N =-(I/C).DELTA.T.sub.1 Equation 1a EQU .DELTA.V.sub.P =-(I/C).DELTA.T.sub.2 Equation 2a
Accordingly, signals SIG1 and SIG2 would be in quadrature if .DELTA.T.sub.1 is equal to .DELTA.T.sub.2. From equations 1a and 2a, .DELTA.T.sub.1 is equal to .DELTA.T.sub.2 if voltage V.sub.N is equal to V.sub.P, or (V.sub.N -V.sub.P) is equal to zero. Thus, the quadrature condition is detected by sampling the differential voltage at node N and node P and comparing the sampled voltage (V.sub.P -V.sub.N) value to zero. That is, input signals SIG1 and SIG2 are in quadrature if the difference between the sampled voltages is zero.
The above described technique for detecting quadrature condition can be effectively used only if integrated voltages .DELTA.V.sub.N and .DELTA.V.sub.P remain well-defined and preferably constant over time periods .DELTA.T.sub.1 and .DELTA.T.sub.2. The integrated voltage is described by the following generalized equation: EQU .DELTA.V=(I/C)*.DELTA.T Equation 3
where ".DELTA.V" refers to the integrated voltage, "I" refers to the bias current provided by the bias current source, "C" refers to the capacitance value, and ".DELTA.T" refers to a given time interval when one switch is closed and the other switch is open. From the above equation, in order to maintain a constant integrated voltage, the ratio of the bias current to the capacitance (i.e., I/C) must remain constant over time intervals .DELTA.T1 and .DELTA.T2. In order to maintain a constant bias current to capacitance (i.e., I/C) ratio, either the bias current I and the capacitance value C must remain constant over time period .DELTA.T, or variations in the value of the bias current I and capacitance C must track and therefore cancel each other.
It is, however, difficult in integrated circuit implementations of quadrature phase detectors to achieve a constant bias current due to variations in temperature, supply voltage and process parameters. Prior art implementations have shown that a bias current can vary up to 100% from its nominal value due to effects of variations in temperature, voltage and processing techniques. Such variations are not acceptable for constructing accurate quadrature phase detectors.
In addition to variations in bias current, the capacitance value of the capacitive elements may also fluctuate in response to changes in temperature, voltage and process parameters. In integrated circuits using CMOS technology, capacitors are typically made of a MOS structure as shown in FIG. 4. The effective capacitance for the MOS capacitive element depicted in FIG.4 is given by: EQU C=C.sub.ox *(W*L) Equation 4
where, "C" is the capacitance value of the MOS structure, "C.sub.ox " is the oxide capacitance per unit area of the transistor channel region, and "(W*L)" is the area of the MOS device. The oxide capacitance "C.sub.ox " varies with variations in process and thus the effective capacitance of the MOS device varies. As a result of variations in the capacitance value, a constant integrated voltage cannot be maintained during time intervals .DELTA.T.sub.1 and .DELTA.T.sub.2, resulting in inaccurate determination of quadrature conditions.
In an effort to provide a constant and stable bias current, prior art techniques have used band-gap bias current generators. However, band-gap based bias current generators require resistor elements and bipolar junction transistors (BJTs) which are not optimally available in a CMOS process. Further, even though band-gap current generators provide a stable current, the problems associated with variations in capacitance values still persist.
Thus, it is desirable to provide a phase detector which minimizes inaccuracies caused by variations in power supply voltage, temperature and/or process parameters.